Semiconductor value chain
| Stage | Function | Key Players | Fabless? | Notes |
| 1. Raw Materials | Supplies silicon wafers, specialty gases, and chemicals for chip fabrication. | Shin-Etsu, Sumco, Air Liquide, Linde, Wacker Chemie | ❌ | Critical upstream suppliers; highly concentrated market. |
| 2. EDA & IP Design | Develops electronic design automation (EDA) tools and IP cores for CPUs, GPUs, etc. | Arm, Synopsys, Cadence, Imagination Tech, Alphawave | ✅ (IP only) | Arm licenses CPU IP; Synopsys/Cadence offer EDA software + interface IP. |
| 3. Chip Design (Fabless) | Designs complete chips (SoCs, MCUs) using IP blocks; outsources manufacturing. | Broadcom, Qualcomm, Nvidia, AMD, MediaTek, Marvell, Raspberry Pi (RP2040), Apple, Tesla, Google (TPU) | ✅ | Relies on IP from Stage 2 and foundries in Stage 4; core of fabless model. |
| 4. Foundry (Fabrication) | Manufactures chips on silicon wafers using lithography and process nodes. | TSMC, Samsung Foundry, Intel Foundry, GlobalFoundries, SMIC | ❌ | TSMC dominates advanced nodes (3nm, 5nm); Intel Foundry re-entering market. |
| 5. OSAT (Packaging & Testing) | Packages silicon into final chip form; conducts electrical testing and reliability screening. | ASE Group, Amkor, JCET, Powertech Technology, STATS ChipPAC | ❌ | Required for yield verification and physical robustness before shipping to OEMs. |
| 6. OEM / Device Assembly | Integrates chips into boards and devices (PCs, phones, dev kits, IoT modules). | Apple, Dell, Raspberry Pi, Asus, Sony, Arduino, Lenovo, Xiaomi | Mixed | Some also design chips (e.g., Apple, Raspberry Pi); others source externally. |
| 7. End Users | Consumers, enterprises, data centers, and industrial clients that use the final product. | Amazon, Meta, governments, telecoms, retail buyers, EV manufacturers | N/A | Demand drives upstream innovation and production volume. |
Most Technical Stages (Ranked by Engineering Intensity)
1. Foundry (Fabrication) – Step 4
- Why: Requires atomic-scale precision, cleanroom environments, and multi-billion-dollar equipment (e.g., EUV lithography from ASML).
- Key Technologies: EUV lithography, FinFET/GAAFET transistors, chemical-mechanical polishing, doping, etching.
- Players: TSMC, Samsung Foundry, Intel Foundry, SMIC.
- Note: Only a few companies in the world can operate at bleeding-edge nodes (3nm and below).
2. EDA & IP Design – Step 2
- Why: Involves the creation of reusable, highly optimized building blocks for chips. Must be correct-by-construction and highly configurable.
- Key Technologies: Formal verification, RTL synthesis, IP reuse, power/performance/area trade-offs.
- Players: Arm, Synopsys, Cadence.
- Note: Mistakes here cascade through the chain; IP must be universally portable and silicon-proven.
3. Chip Design (Fabless) – Step 3
- Why: Combines IP into complex SoCs (often billions of transistors), balancing power, area, performance, cost.
- Key Technologies: System-level architecture, RTL, DFT, floorplanning, simulation.
- Players: Nvidia, AMD, Qualcomm, Apple, Broadcom.
- Note: Designs must match physical design constraints from fabs and pass dozens of verification layers.
Less Technical (But Still Critical) Stages
- OSAT (Step 5): Technical in terms of precision packaging and thermal design, but not at the same frontier as lithography or chip design.
- OEM / Integration (Step 6): Focuses more on system integration, cost engineering, and logistics.
- Raw Materials (Step 1): Chemically intensive but standardized.
- End Users (Step 7): No technical role in chip creation.