Long before a chip exists, engineers must make a wager about the software it will run. They decide where to spend silicon area, how data will move and which calculations deserve specialised hardware. By the time the design reaches production, the market may have changed. Successful chip design combines technical foresight with the commercial discipline to make those expensive decisions pay across millions of devices or years of computing workloads.
The investment question
The central question is whether the designer owns a durable computing platform or a temporary performance advantage. A faster processor can win a benchmark. A platform also needs software, libraries, developer familiarity, reliable supply and a deployment path that customers can operate economically. Those complements explain why a technically credible competitor may take years to gain significant production adoption.
AI makes this distinction particularly consequential. Merchant GPUs, hyperscaler accelerators and specialised inference designs can all grow, while capturing very different margins. The attractive business is the one whose delivered value exceeds the cost of its entire supporting system and whose relevance survives changes in models. Raw chip shipments tell only part of that story.
How chip design works
Architecture defines the machine: instruction handling, compute engines, cache, memory interfaces and communication. Engineers then implement and verify the logic, translate it into physical structures and check timing, power and manufacturability. Tape-out releases a design for manufacture; it does not guarantee a functioning, qualified product. Silicon validation, packaging, firmware and customer testing still stand between a design milestone and recurring revenue.
The scarce resource is not simply transistor count. Silicon area, power delivery, heat removal and memory bandwidth must be allocated together. A design with additional arithmetic units may deliver little benefit if those units cannot receive data quickly enough. Conversely, adding memory capacity or improving communication can raise useful performance without a proportional increase in peak calculations.
Chiplets divide a product into multiple dies, potentially allowing compute, input/output and other functions to use different manufacturing processes. This can improve design reuse and reduce some large-die manufacturing risks. It also introduces interconnect overhead, packaging cost and additional testing. Chiplets are an engineering trade-off, not a universal guarantee of cheaper chips.
Market structure and competitive advantage
| Business model | Examples | Where value is captured |
|---|---|---|
| Merchant computing platforms | NVIDIA, AMD | Hardware, software adoption and system integration |
| Custom silicon partners | Broadcom, Marvell | Architecture support, implementation and supply execution |
| Captive chip design | Google, Amazon, Apple | Better economics or differentiation in the parent business |
| Processor intellectual property | Arm | Licensing and royalties, with different capital requirements |
A merchant supplier can spread research over many customers and workloads. A captive designer can optimise around its own software and distribution, accepting a narrower addressable market. A custom silicon partner occupies the space between: the customer controls important requirements, while the supplier contributes implementation expertise, interfaces and production execution. The exact division of intellectual property and risk varies by contract.
Software is a major source of switching friction. Framework compatibility is necessary but insufficient: customers also need optimised kernels, debugging tools, stable numerical behaviour and reliable distributed execution. Google’s Ironwood architecture discussion describes the interaction between its accelerator, interconnect and software. Such integration helps explain competitiveness; vendor performance claims still require workload-specific validation.
Economics: the cost of a useful workload
Chip design has substantial upfront costs: engineering, EDA tools, intellectual property, masks and validation. Successful products spread those costs over volume. A design win can therefore be valuable, but its financial significance depends on production timing, unit volumes, selling prices and how much revenue reflects externally purchased components. Counting announced customers without examining those factors can overstate diversification.
For a custom project, the key distinction is between non-recurring engineering payments and recurring production revenue. The former can compensate development effort; the latter determines the long-run scale of the programme. A programme may ramp sharply and then flatten as the customer shifts to its next design. Revenue visibility consequently depends on a continuing roadmap rather than a single successful tape-out.
Customers should compare cost per completed workload, including hardware depreciation, electricity, networking, memory, software engineering and lost productivity during migration. Illustratively, hardware that costs 20% less but processes 30% fewer equivalent jobs per hour has about 14% higher hardware cost per job at equal utilisation. That calculation deliberately excludes other costs; it shows why price and throughput must be considered together.
AI and hyperscalers: customers become competitors
Hyperscalers possess an unusual advantage: they can design chips around workloads they already control. Google’s TPUs and Amazon’s Trainium demonstrate different implementations of this strategy. They can also expose those chips through cloud services, allowing external customers to consume the technology without buying the physical processor. The cloud platform becomes both a distribution channel and a source of workload information.
The merchant supplier’s defence is breadth and execution. A widely supported platform can handle rapidly evolving models, serve customers across clouds and reduce deployment uncertainty. Custom silicon gains ground when the workload is sufficiently understood and the operator can amortise development across substantial demand. These advantages are conditional; neither business model automatically wins training or inference as an entire category.
The upstream consequences are also important. Custom accelerators still need foundry capacity, high-bandwidth memory, packaging and network connectivity. A shift away from a merchant GPU can preserve demand for shared suppliers while changing the distribution of profit. Investors should map the production chain before treating custom silicon as negative for every incumbent semiconductor business.
Current market debates — September 2026
Recent results show growth across different models. NVIDIA’s 26 August 2026 release reported quarterly revenue of $96.2 billion. Broadcom’s fiscal third-quarter 2026 release reported $16.7 billion of AI semiconductor revenue. Those figures use different business definitions and must not be used to calculate directly comparable accelerator market shares.
The debate is whether custom silicon is mostly expanding the market or beginning to constrain merchant pricing. The constructive merchant case is that demand expands faster than alternatives mature. The custom silicon case is that large customers gain negotiating power as credible internal platforms enter production. Evidence of price concessions, customer migration and sustained deployment matters more than isolated benchmark comparisons.
AMD’s August 2026 results add another dimension: customers can pursue a second merchant ecosystem as well as internal designs. Diversification should be assessed through repeat orders and production software support. A partnership announcement or future deployment target is not equivalent to revenue already earned or computing already delivered.
Structural debates: specialisation and control
The enduring issue is how much specialisation a changing software market can support. Greater specialisation can improve efficiency but reduce flexibility if model architectures change. Programmability and strong compilers soften that trade-off; they do not eliminate physical constraints. Inference itself contains different workloads, from latency-sensitive interactive requests to high-throughput batch processing, with different hardware requirements.
Another debate concerns who owns the system boundary. Designers increasingly coordinate processors, networking and rack architecture because component performance depends on the surrounding system. That can deepen customer reliance, but also invites hyperscalers to design around more open interfaces and alternative suppliers. Customers may accept integration where it improves execution while resisting it where it weakens purchasing leverage.
Finally, supply commitments create commercial risk. Outsourcing manufacturing does not remove exposure to product transitions, cancelled demand or expensive inventory. Strong gross margins should therefore be read alongside inventory, customer concentration and contractual commitments, especially when deployment schedules depend on data-centre power availability.
What to watch
Follow production deployments, repeat customer wins, software maturity, actual workload performance and the cadence of successor products. Separate booked revenue from design wins, and distinguish total company revenue from accelerator-specific exposure. Evaluate purchase commitments against expected demand and manufacturing lead times.
The best evidence of a durable design franchise is a customer choosing its next generation after running the current one at scale. That decision incorporates software, support, reliability and economics that a launch presentation cannot fully reveal.
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Semiconductors & chipmaking — sector overview
Related sectors: AI infrastructure & data centres · Data platforms & analytics
