An AI accelerator can perform an extraordinary number of calculations and still spend valuable time waiting. The problem is often moving the right data to the right place quickly enough. Memory determines how much information a system can hold close to its processors, how rapidly it can be read and how much energy is spent moving it. In AI infrastructure, those constraints can matter as much as the computing engines themselves.
The investment question
The memory investment question is whether AI creates a lasting improvement in industry returns or a particularly powerful phase of a familiar supply cycle. High-bandwidth memory, or HBM, increases technical differentiation and ties suppliers closely to accelerator roadmaps. Yet manufacturers still invest heavily, improve yields and compete for customer qualification. Scarcity today does not establish permanent pricing power.
Our view is that memory must be analysed by product, customer and generation. HBM, conventional server DRAM and NAND storage address different needs and have different supply dynamics. A company can gain an attractive HBM position while remaining exposed to pricing pressure elsewhere. Total revenue growth should therefore be decomposed into bits shipped, realised pricing and product mix.
How memory fits into the system
DRAM provides working memory that loses its contents when power is removed. HBM is a form of DRAM built into stacks and connected through a wide interface, usually close to an accelerator. Conventional server DRAM supplies larger pools of system memory. NAND stores data persistently and is the underlying medium in solid-state drives. These are complementary layers rather than interchangeable products.
Capacity answers how much data fits; bandwidth answers how much can move each second; latency answers how long an individual access takes. These characteristics interact. A model that does not fit in available accelerator memory may require additional devices or offloading. A model that fits can still be limited by the speed at which its weights and intermediate data are accessed.
Micron’s HBM4 product description sets out the capacity and bandwidth role of the technology. Physical stacking and dense connections increase integration complexity. Suppliers must control die quality, bonding, thermal behaviour and final qualification. A memory stack meeting an advertised speed is not automatically qualified for every accelerator package or operating condition.
Market structure and competitive advantage
| Memory layer | Principal purpose | Competitive question |
|---|---|---|
| HBM | Feed accelerators at high bandwidth | Qualified performance, power and supply |
| Server DRAM | Hold application and system working data | Cost, capacity and platform qualification |
| NAND and enterprise SSDs | Store datasets, checkpoints and application data | Cost per usable capacity, endurance and controller capability |
SK hynix, Samsung and Micron are central participants in DRAM and HBM, while NAND has a different competitive landscape that also includes suppliers such as Kioxia and Sandisk. Market positions should be measured within the relevant product and generation. A supplier’s total DRAM capacity is not the same as its qualified HBM output.
Customer qualification can support differentiated economics. Accelerators are designed around specific memory and packaging requirements, making a late substitution costly. But large customers have strong incentives to qualify multiple suppliers. A successful challenger can improve supply resilience and alter pricing even if the incumbent retains a technical lead on selected dimensions.
Economics: bits, yields and product mix
Memory revenue is approximately bits shipped multiplied by realised price per bit, adjusted for product mix and the way finished products are sold. Process improvements can increase bits per wafer and reduce cost. More complex products can command higher prices while also requiring more manufacturing and packaging resources. The margin outcome depends on both sides of that equation.
HBM can affect conventional DRAM supply because it competes for manufacturing resources and adds demanding integration steps. The precise trade-off varies by design, process and yield; applying a fixed industry-wide conversion ratio would be misleading. What matters is how suppliers allocate capacity and how quickly qualified output grows, rather than simply the number of new factory buildings announced.
Illustratively, if bit shipments rise 15% but average realised price falls 20%, revenue falls 8% before mix effects: 1.15 multiplied by 0.80 equals 0.92. This is not a forecast. It explains why healthy end-demand growth can coexist with falling memory revenue when supply catches up and prices adjust.
Capital expenditure complicates the picture further. Technology transitions and additional capacity consume cash before the resulting output is sold. Attractive current margins can encourage investment across the industry, laying the groundwork for a later correction. Long-term agreements may improve visibility, but assess their volume commitments, pricing mechanisms and enforceability rather than assuming that contracted demand removes all cyclical risk.
AI and hyperscalers: more than a training story
Training requires memory for model parameters, gradients and other intermediate state. Inference requires model weights and, for many language-model serving systems, a cache associated with the context being processed. Longer contexts and more simultaneous requests can increase memory needs. The effect depends on the model architecture, numerical precision, batching and serving implementation.
Reasoning and agentic applications can increase the amount of computation performed per user task, but the memory consequence is not a universal multiplier. Quantisation, caching, more efficient attention implementations and workload scheduling can reduce the resources required for a fixed task. The demand debate must therefore combine architectural intensity with the growth in actual usage.
Hyperscalers influence memory through merchant GPU purchases and custom accelerator programmes. A change in accelerator supplier can preserve HBM demand while changing the memory configuration and qualification requirements. The surrounding data platform also needs server DRAM and storage for retrieval, databases and checkpoints. AI exposure extends across the hierarchy, but each layer earns a different price for solving its particular constraint.
Current market debates — September 2026
SK hynix’s July 2026 results describe strong AI-related memory demand and high-value product mix. Samsung’s second-quarter 2026 release similarly points to server demand and continued AI infrastructure investment. These are reported outcomes and management expectations, not evidence that supply will remain tight indefinitely.
The immediate technology debate concerns HBM4 ramps and the distribution of qualified supply. Micron has announced high-volume HBM4 production for NVIDIA’s Vera Rubin platform. Production announcements should be separated from achieved shipment volume, customer acceptance and the profitability of the ramp. A supplier can improve its technological position before the full benefit appears in financial results.
The constructive case is that expanding inference and richer memory configurations absorb new capacity. The countercase is that improved yields, additional qualified suppliers and slower deployment growth reduce scarcity premiums. Watch whether pricing remains firm as supply broadens, and whether conventional DRAM and NAND markets confirm or contradict the HBM narrative.
Structural debates: differentiation versus cyclicality
The first structural debate is whether HBM resembles a specialised engineered component more than a commodity memory product. Close customer integration, demanding qualification and power efficiency support differentiation. Industry investment, standardisation and customers’ desire for multiple suppliers preserve competitive pressure. Both characteristics can coexist, producing better economics than older memory cycles without eliminating volatility.
Second, memory and logic integration may redistribute value. More capable base dies and closer coordination with foundries can increase performance, while changing which supplier controls design, manufacturing and packaging. The opportunity should be traced through the specific architecture instead of assuming the memory vendor captures every additional dollar of complexity.
Third, the system may use different memory tiers more intelligently. Software can trade latency, capacity and cost by moving less frequently used data away from expensive accelerator memory. This does not make HBM unnecessary; it changes the quantity required per workload. The long-run winners must improve cost and energy efficiency as well as peak bandwidth.
What to watch
Track HBM qualification and shipment ramps, memory capacity per deployed accelerator, conventional DRAM pricing, NAND supply discipline and inventory throughout the channel. Compare capital expenditure with expected bit growth and examine whether cash generation remains strong after factory investment.
The most convincing memory thesis survives a scenario in which shortages ease. It should explain why a supplier retains a cost, performance or customer-integration advantage when buyers regain more choice.
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